SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION MASK LAYOUT
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United States of America
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Feb 6, 2025
app pub date -
Oct 23, 2024
filing date -
Oct 23, 2024
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Abstract
A deep trench layout implementation for a semiconductor device is provided. The semiconductor device includes an isolation film with a shallow depth, an active area, and a gate electrode formed in a substrate; a deep trench isolation surrounding the gate electrode and having one or more trench corners; and a gap-fill insulating film formed inside the deep trench isolation. The one or more trench corners is formed in a slanted shape from a top view.
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