REDUCTION OF SIZE OF EDGE CELL REGION IN MEMORY DEVICES
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United States of America
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Feb 6, 2025
app pub date -
Jan 4, 2024
filing date -
Jan 4, 2024
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Abstract
An integrated circuit (IC) device has a memory region in which a plurality of memory cells is implemented. Each of the memory cells has a first dimension in a first horizontal direction. The IC device includes an edge region bordering the memory cell region in the first horizontal direction. The edge region has a second dimension in the first horizontal direction. The second dimension is less than or equal to about 4 times the first dimension. The IC device is formed by revising a first IC layout to generate a second IC layout. The second IC layout is generated by shrinking a dimension of the edge region in the first horizontal direction.
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