SYSTEM AND METHOD FOR CALIBRATING WEIGHTING ERRORS IN SPLIT CAPACITANCE SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Feb 6, 2025
app pub date -
Sep 22, 2023
filing date -
Sep 22, 2023
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
The present disclosure relates to the field of microelectronics and solid-state electronics, and in particular to a calibration system and method for weighting errors brought about by parasitic capacitance in split capacitor-based successive approximation analog-to-digital converters. The method uses an MSB array that does not add additional capacitors, only a switch SM to reduce the comparator design difficulty. Meanwhile, an LSB array may add a calibration DAC array CA including a binary array of P-bit unit capacitors, a calibration structure Cfraq, and a ground switch Sk. The calibration structure Cfraq includes four unit capacitors and two switches S1 and S2. By controlling the switches S1 and S2 different capacitance values can be generated to reduce the chip area consumption. This structure can reduce the error to LSB/4 and the weighting error of the ADC, and increases the effective number of bits of the ADC without excessively increasing comparator gain.
First Claim
Other Claims data not available
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
- 0 Citation Count
- H03M Class
- 0 % this patent is cited more than
- < 1 Age