SELECTIVELY-ACTIVATED TERMINATION CIRCUITRY, AND ASSOCIATED SYSTEMS, METHODS, AND DEVICES
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United States of America
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Issued Date -
Feb 6, 2025
app pub date -
Oct 25, 2024
filing date -
Oct 25, 2024
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Abstract
Memory systems are disclosed. A memory system may include a plurality of memory devices and a controller in communication with the plurality of memory devices. The controller may be configured to load respective select information to at least some memory devices of the plurality of memory devices. Each memory device of the at least some memory devices may be configured to store its respective select information. Further, each memory device of the at least some memory devices may be configured to adjust, based on the stored select information and in response to receipt of a signal at the memory device, an impedance characteristic of the memory device during at least a portion of a memory device operation of another memory device of the plurality of memory devices. Associated methods and devices are also disclosed.
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