Parallel decoding method, processor, chip and electronic device
Number of patents in Portfolio can not be more than 2000
United States of America
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Feb 6, 2025
app pub date -
Feb 27, 2023
filing date -
Feb 27, 2023
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Abstract
Embodiments of the present disclosure provide a method for parallel decoding which is applied to a processor including at least a first decoder cluster and a second decoder cluster, the second decoder cluster being provided with at least one shared decoder shared by the first decoder cluster. In the method if a quantity of a plurality of instructions is greater than a quantity of decoders in the first decoder cluster, assigning first instructions with a quantity corresponding to the quantity decoders of the first decoder cluster in the plurality of instructions to a decoder in the first decoder cluster for decoding, and assigning second instructions other than the first instructions in the plurality of instructions to the at least one shared decoder for decoding; writing, micro-ops obtained by decoding the first instructions and micro-ops obtained by decoding the second instructions into the first micro-op queue.
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