PLANAR FERROELECTRIC MEMORY DEVICE
Number of patents in Portfolio can not be more than 2000
United States of America
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Issued Date -
Jan 30, 2025
app pub date -
Oct 16, 2024
filing date -
Oct 16, 2024
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Abstract
Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.
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