Importance

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Abstract

Disclosed is an analog-to-digital converter (ADC) circuit for digitizing a pixel signal into a digital signal of positive integer (N) bits. The ADC includes a ramp generator, a clock, a comparator, and a counter. A system clock signal allows the ramp generator to generate a ramp signal and the clock generator to generate first to N-th clock signals. The comparator generates a comparison signal based on a comparison of the pixel signal, received from a pixel array, and the ramp signal. The counter includes an additional latch circuit and first to N-th latch circuits. The additional latch circuit generates an additional binary signal based on the system clock signal and the comparison signal, and the first to N-th latch circuits generate first to N-th latch signals based on the comparison signal and corresponding clock signal.

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First Claim