BIASING CIRCUIT FOR RADIO FREQUENCY AMPLIFIER
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United States of America
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Issued Date -
Jan 30, 2025
app pub date -
Jul 25, 2023
filing date -
Jul 25, 2023
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Abstract
A biasing circuit for biasing an output transistor in a radio frequency (RF) amplifier includes a first field-effect transistor (FET) monolithically integrated with the output transistor, the first FET being connected to the output transistor in a current mirror configuration, such that a gate-to-source voltage of the first FET is the same as a gate-to-source voltage of the output transistor, and a drain current in the first FET is matched to a drain current in the output transistor and scaled proportionally according to a size of the first FET relative to a size of the output transistor. The biasing circuit further includes a voltage divider integrated with the first FET and connected to a current source, the voltage divider being configured to generate a voltage that is substantially independent of process, voltage and/or temperature variations for controlling the drain current in the first FET.
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