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Abstract

Architectures of 3D memory arrays, systems, and methods regarding the same are described. An array may include a substrate arranged with conductive contacts in a geometric pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, a sacrificial layer may be deposited in a trench that forms a serpentine shape. Portions of the sacrificial layer may be removed to form openings, into which cell material is deposited. An insulative material may be formed in contact with the sacrificial layer. The conductive pillars extend substantially perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. A chalcogenide material may be formed in the recesses partially around the conductive pillars.

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First Claim