VERTICAL MEMORY DEVICE WITH A DOUBLE WORD LINE STRUCTURE
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United States of America
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Issued Date -
Jan 30, 2025
app pub date -
Oct 10, 2024
filing date -
Oct 10, 2024
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Abstract
A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.
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