BIT LINE READING CIRCUIT, MEMORY, AND ELECTRONIC DEVICE
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United States of America
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Issued Date -
Jan 30, 2025
app pub date -
Oct 18, 2024
filing date -
Oct 18, 2024
priority date (Note) -
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Abstract
This disclosure relates to a bit line reading circuit, a memory, and an electronic device. An example bit line reading circuit includes a bit line connected to a ferroelectric memory cell. The bit line reading circuit further includes a reference line, a sense amplifier, and a precharge circuit. The sense amplifier and the precharge circuit are separately connected to the bit line and the reference line. The bit line reading circuit further includes a first switch connected to the bit line between the sense amplifier and the precharge circuit, and a second switch connected to the reference line between the sense amplifier and the precharge circuit.
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