POWER REDUCTION BY REMOVAL OF REDUNDANCY IN CLOCK PATHWAYS OF VLSI CIRCUITS
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United States of America
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Issued Date -
Jan 30, 2025
app pub date -
Jul 24, 2023
filing date -
Jul 24, 2023
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Abstract
Methods, systems, and products for power reduction by removal of redundancy in clock pathways of VLSI circuits includes: calculating, based on a circuit design data file, a timing budget for an LCB (local clock buffer) and an associated group of latches receiving a clock signal from the LCB, where the circuit design data file includes a structural representation of a circuit design and timing data, identifying, based on the timing budget, a delay element to remove, the delay element included within a delay element chain associated with the LCB, and removing the delay element from the circuit design.
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