POLISHING PAD WITH REDUCED DEFECT AND METHOD OF PREPARING A SEMICONDUCTOR DEVICE USING THE SAME
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Jan 30, 2025
app pub date -
Jun 19, 2024
filing date -
Jun 19, 2024
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
In the polishing pad according to an embodiment, the particle size of debris obtained during conditioning and the zeta potential of a debris solution are adjusted to specific ranges. As a result, it is possible to minimize the occurrence of defects and scratches during a CMP process while reducing the size of debris, thereby maintaining excellent physical properties and performance of the polishing pad.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully