THREE-DIMENSIONAL DEVICE AND MANUFACTURING METHOD THEREOF
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United States of America Patent
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Issued Date -
Jan 23, 2025
app pub date -
Oct 7, 2024
filing date -
Oct 7, 2024
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Abstract
When testing a memory chip, the memory chip is determined to be defective if even a portion of the memory chip is defective, and is discarded, which lowers the yield of the three-dimensional memory device. A three-dimensional device is provided comprising a plurality of stacked circuit chips each having one or more circuit blocks in each of a plurality of divided regions obtained by dividing a circuit plane and an interconnect portion communicatively connected, for each group of circuit blocks included in each of the divided regions overlapping in a stacking direction in the plurality of circuit chips, to a predetermined number of circuit blocks sorted from the circuit blocks within the group.
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