ACCESS LINE FORMATION FOR A MEMORY ARRAY
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United States of America Patent
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Issued Date -
Jan 23, 2025
app pub date -
Jul 30, 2024
filing date -
Jul 30, 2024
priority date (Note) -
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status (Latency Note)
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Abstract
Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.
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