PLATED VIA-IN-VIA VERTICAL CONNECTION
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United States of America Patent
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Issued Date -
Jan 23, 2025
app pub date -
Jul 19, 2023
filing date -
Jul 19, 2023
priority date (Note) -
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Abstract
A method of manufacturing a via-in-via vertical interconnect in a printed circuit board (PCB), including: drilling a first hole through the PCB; drilling a second hole into a top side of the PCB; plating the first hole and the second hole with a conductive material to form an outer layer; drilling a third hole through the PCB wherein a portion of the plating is removed between the first hole and the second hole; filling the first, second, and third holes with an outer filler; drilling a fourth hole through the outer filler; plating the fourth hole with a conductive material to form an inner layer; filling the fourth hole with an inner filler; forming a via-in-via pad on top of the inner filler connected to the inner layer; and drilling a fifth hole through the bottom of the PCB along the fourth hole to remove a portion of the inner filler and inner layer wherein the top of the fifth hole is below the internal layer.
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