Continuously changing system clock in a packet processing module based on load determined by deterministic feedback signals
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United States of America Patent
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Issued Date -
Jan 23, 2025
app pub date -
Dec 18, 2023
filing date -
Dec 18, 2023
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Abstract
A packet processing module includes circuitry configured to receive feedback signals from each of N first-in, first-out (FIFOs), N is an integer that is greater than or equal to 1, determine a clock speed for the packet processing module based on the received feedback signals, and program a phase lock loop (PLL) based on the determined clock speed where the PLL provides a module clock at the determined clock speed to a packet processing circuit which is configured to receive and process packets from the N FIFOs. The feedback signals are a deterministic representation of processing needed for the packet processing circuit given a current state of packets available.
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