Importance

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Abstract

A circuit for a phase-locked loop is described herein. The circuit includes a phase frequency detector configured to determine a phase error, a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error, and a controller coupled to the phase frequency detector and to the loop filter. The controller is configured to receive the phase error, detect a behavior of the phase error, and, responsive to the behavior of the phase error, perform a response that includes causing the phase frequency detector to adjust the phase error and causing the loop filter to adjust the clock control signal. Thus, the circuit may reduce settling time, overshoot, and/or undershoot in an output clock generated based on the clock control signal.

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First Claim