Digitally Calibrated Programmable Clock Phase Generation Circuit
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United States of America Patent
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N/A
Issued Date -
Jan 23, 2025
app pub date -
Oct 8, 2024
filing date -
Oct 8, 2024
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
An integrated circuit that includes a generating circuit is described. During operation, the generating circuit may provide an edge clock having a target phase within a clock period of an input clock, where the generating circuit does not include a delay-locked loop (DLL). For example, the generating circuit may include a gated ring oscillator that provides a reference clock having a first fundamental frequency that is larger than a second fundamental frequency of the input clock. Note that the gated ring oscillator may be programmable to adjust the first fundamental frequency within a predefined range of values. Moreover, the generating circuit may include a control circuit that determines a reference count of a number of edges of the reference clock within a reference period of the reference clock.
First Claim
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