COMPUTATION IN-MEMORY USING 6-TRANSISTOR BIT CELLS
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United States of America Patent
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Issued Date -
Jan 23, 2025
app pub date -
Sep 12, 2024
filing date -
Sep 12, 2024
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Abstract
A device includes a first bit cell, a second bit cell, and a multiply and average (MAV) circuit. The MAV circuit includes a first selection circuit and a second selection circuit. The first selection circuit has a first selection input and coupled to first and second capacitor terminals, and the first selection circuit is configured to, responsive to a state of the first selection input, set respective states of the first and second capacitor terminals based on a state of the first bit cell. The second selection circuit has a second selection input and is coupled to the first and second capacitor terminals. The second selection circuit is configured to, responsive to a state of the second selection input, set the respective states of the first and second capacitor terminals based on a state of the second bit cell.
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