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Abstract

Disclosed is a sub-sampling phase-locked loop circuit capable of avoiding harmonic locking, which comprises a harmonic suppression sampling charge pump module, a filter module and a voltage-controlled oscillator module; a reference clock signal and differential signals are respectively accessed to an input end of the harmonic suppression sampling charge pump module, an output signal of an output end of the harmonic suppression sampling charge pump module is accessed to a filter and then accessed to an input of a voltage-controlled oscillator, an output end of the voltage-controlled oscillator module outputs differential signals as the differential signals accessed to the input end of the harmonic suppression sampling charge pump module, output signals of the voltage-controlled oscillator module are used as final outputs of the phase-locked loop circuit, and the output differential signals are synchronous with the reference clock in phase at the same time.

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First Claim