STRESS LINERS IN SEMICONDUCTOR DEVICES
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United States of America
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Issued Date -
Jan 16, 2025
app pub date -
Nov 17, 2023
filing date -
Nov 17, 2023
priority date (Note) -
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Abstract
A semiconductor device and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a nanostructured channel region disposed on the substrate, a gate structure surrounding the nanostructured channel region, a source/drain (S/D) region disposed adjacent to the nanostructured channel region, an etch stop layer (ESL) disposed on the S/D region, a stress liner disposed on the etch stop layer and configured to provide compressive stress in the nanostructured channel region, an inter-layer dielectric (ILD) layer disposed on the stress liner, and a contact structure disposed in the S/D region, ESL, stress liner, and ILD layer.
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