MEMORY DEVICE AND METHOD FOR CALIBRATING IMPEDANCE THEREOF
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United States of America
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Issued Date -
Jan 16, 2025
app pub date -
Jan 31, 2024
filing date -
Jan 31, 2024
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Abstract
A memory device includes: a memory cell array; an input/output circuit controlling inputting and outputting data stored in the memory cell array; an impedance calibration circuit generating an impedance calibration code based on an external resistor connected to an impedance pad for application to the input/output circuit as an applied impedance calibration code; and a calibration control circuit comparing a new impedance calibration code received from the impedance calibration circuit with a calibration code range for generating a calibration code update flag when the new impedance calibration code is included in the calibration code range. The impedance calibration circuit updates the applied impedance calibration code with the new impedance calibration code when receiving the calibration code update flag.
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