REDUCED LOGIC GATE ACCUMULATORS
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Jan 16, 2025
app pub date -
May 14, 2024
filing date -
May 14, 2024
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
An apparatus includes a memory having memory elements configured to store bits of a count value. The apparatus also includes sense amplifiers configured to read the bits of the count value from the memory elements and write amplifiers configured to write the bits of the count value to the memory elements. The apparatus further includes at least one logic gate configured to generate at least one feedback bit based on the count value stored in the memory elements. Some of the sense amplifiers are coupled to some of the write amplifiers in order to read and shift a subset of the bits of the count value and store the shifted subset of the bits of the count value in the memory. The shifted subset of the bits of the count value and the at least one feedback bit form an updated count value in the memory elements.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully