HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20250021235A1
SERIAL NO

18794280

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Abstract

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Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INCSAN JOSE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Horn, Stephen Raleigh, US 10 41
Miller, Micheal Raleigh, US 2 0
Shallal, Aws Cary, US 35 218

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