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Abstract

Devices, e.g., hardware accelerators, and systems are operable to perform a two-dimensional (2D) fast Fourier transform (FFT) on an M×N element array. The hardware accelerator has log₂ M×N pipeline stages including an initial group of log₂ M stages and a final group of log₂ N stages. Each stage includes a butterfly unit, a FIFO buffer coupled to the butterfly unit, and a multiplier coupled to the butterfly unit and to an associated twiddle factor table. The hardware accelerator also includes butterfly control logic to provide elements of the M×N element array to the initial group of stages in an N direction of the array, and twiddle factor addressing logic to, for the twiddle factor tables of the initial group of stages, apply an indexed entry of the twiddle factor table to the associated multiplier. The indexed entry begins as a first entry and advances by N entries after every N cycles.

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First Claim