High-speed CMOS pixel detector
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United States of America
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Issued Date -
Jan 9, 2025
app pub date -
Jul 3, 2024
filing date -
Jul 3, 2024
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Abstract
A high-speed CMOS pixel detector is provided, which includes a plurality of super pixel modules, where each super pixel module includes an array of N×M super pixel cells and a digital readout logic circuit connected to the N×M super pixel cells, and data is output between the super pixel modules via asynchronous control logic; and peripheral modules, including at least an EoC module, a peripheral readout module, and a peripheral data transmission module connected in sequence, where the EoC module is connected to the super pixel modules. This application adopts a structure in which a plurality of super pixel cells are integrated, allowing for upgrading of a serial sparse readout mode to a parallel sparse readout mode, thereby greatly improving a readout rate, enabling a plurality of pixels to share resources, and reducing pixel dimensions.
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