CLOCK DOUBLER, A CLOCK GENERATING DEVICE AND A SEMICONDUCTOR SYSTEM USING THE SAME
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United States of America
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Jan 9, 2025
app pub date -
Nov 9, 2023
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Nov 9, 2023
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Abstract
A clock doubler includes a first triggering circuit, a second triggering circuit, and a gating circuit. The first triggering circuit generates a first trigger clock signal using rising edges of a first phase clock signal and a second phase clock signal. The second triggering circuit generates a second trigger clock signal using rising edges of a third phase clock signal and a fourth phase clock signal. The gating circuit gates the first and second trigger clock signals to generate an output clock signal the frequency of which is twice the frequency of clock signals provided to the triggering circuits.
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