INTEGRATED CIRCUIT SIMULATOR FOR DEGRADATION ESTIMATION AND TIME-OF-FAILURE PREDICTION
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Jan 9, 2025
app pub date -
Nov 15, 2022
filing date -
Nov 15, 2022
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A method including: Receiving timing data of multiple data paths of an integrated circuit (IC) design. Simulating degradation of the multiple data paths over a period of time, wherein the timing data serve as a baseline of the simulated degradation, and wherein the simulation includes: simulating effects of operational conditions on the multiple data paths, wherein the operational conditions comprise: temperature, voltage, and frequency; simulating an effect of at least one physical degradation phenomenon on the multiple data paths, wherein the at least one physical degradation phenomenon is negative-bias temperature instability (NBTI), hot carrier injection (HCI), electromigration (EM), and/or time-dependent dielectric breakdown (TDDB); and simulating operation of a margin measurement circuit which is embedded in the IC design and monitors the multiple data paths, wherein the margin measurement circuit, in the simulated operation, outputs a time series of values of a worst-case remaining margin of the multiple data paths.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully