SEMICONDUCTOR DEVICE
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United States of America
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Issued Date -
Dec 26, 2024
app pub date -
Jun 17, 2024
filing date -
Jun 17, 2024
priority date (Note) -
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status (Latency Note)
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Abstract
A switch element configured to apply a voltage to and block a voltage from a gate electrode of a memory cell is provided. The E-type transistor includes a gate insulating film with a thickness in a range of 13 nm to 50 nm, a first current terminal, and a second current terminal. The E-type transistor includes a first source diffusion layer and a first drain diffusion layer having a first n-type impurity density and formed in a vicinity of the gate electrode; and a second source diffusion layer and a second drain diffusion layer having a second n-type impurity density higher than the first n-type impurity density. The second current terminal of the E-type transistor is electrically connected to a voltage source configured to provide a voltage equal to or larger than 15 V.
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