RECEIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME
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United States of America
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Dec 26, 2024
app pub date -
Oct 16, 2023
filing date -
Oct 16, 2023
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Abstract
A receiver includes a decision feedback equalizer therein. The equalizer, which includes a cascaded arrangement of a first stage having a first plurality of summers therein and a second stage having a second plurality of summers therein, is configured to: (i) generate a compensated data signal by summing a current value of a data signal and a plurality of feedback signals, in response to a plurality of selection signals, (ii) generate a sampled signal including a decision value by sampling bits of the compensated data signal, in response to a plurality of divided strobe signals, and (iii) generate the feedback signals in response to a plurality of weights, the sampled signal, and at least one delayed version of the sampled signal.
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