PHASE-LOCKED LOOP CIRCUIT WITH FREQUENCY HOLDING AND REFERENCE FREQUENCY SMOOTH SWITCHING

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United States of America

APP PUB NO 20240429923A1
SERIAL NO

18822556

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Abstract

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A phase-locked loop circuit comprises a clock signal loss detection module, a time-to-digital converter, a digital-to-time converter, a phase discriminator, a charge pump, a loop filter, a comparator, a voltage-controlled oscillator, a frequency divider, a reference voltage generation module and a switch; a capacitor array of the voltage-controlled oscillator is adjusted by using an output of the comparator, so that a control voltage Vctrl of the voltage-controlled oscillator is constantly equal to a reference voltage after a phase-locked loop is locked and does not change along with a change of a PVT condition; after a reference clock signal is lost, the circuit directly adopts the reference voltage as the control voltage of the voltage-controlled oscillator, and after the reference clock signal is re-accessed, an output delay of the digital-to-time converter is adjusted, clock edge alignment of a new reference clock signal and a feedback clock signal is realized.

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Patent Owner(s)

Patent OwnerAddress
MAGNICHIP CO LTD5-6 FLOOR BUILDING A NO 73 HUACHUANG ROAD JIANGBEI NEW AREA NANJING 210000

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
ZHANG, Hao Nanjing, CN 1170 5565
ZHAO, Chao Nanjing, CN 139 838

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