DATA RECEIVER CIRCUIT INCLUDING LOOP-UNROLLED PHASE DECISION FEEDBACK EQUALIZER WITH DUTY CYCLE CONTROL
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United States of America
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Issued Date -
Dec 26, 2024
app pub date -
Jun 23, 2023
filing date -
Jun 23, 2023
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status (Latency Note)
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Abstract
A data signal receiver circuit, including: a comparator configured to generate a first data signal based on a comparison of an input data signal and a reference voltage, wherein the first data signal includes a first logic low pulse and a first logic high pulse; and a duty cycle control circuit configured to generate: a second data signal based on the first data signal, wherein the second data signal includes a second logic low pulse responsive to the first logic low pulse, wherein the second logic low pulse has a width greater than a unit interval (UI); and a third data signal based on the first data signal, wherein the third data signal includes a second logic high pulse responsive to the first logic high pulse, wherein the second logic high pulse has a width greater than the UL.
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