DATA BUFFER CIRCUIT STRUCTURE, LAYOUT STRUCTURE OF MULTIPLE DATA BUFFER CIRCUITS, AND MEMORY
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United States of America
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Issued Date -
Dec 26, 2024
app pub date -
Aug 30, 2024
filing date -
Aug 30, 2024
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Abstract
A data buffer circuit structure, a layout structure of multiple data buffer circuits, and a memory. The data buffer circuit structure includes a first amplification circuit, a second amplification circuit, a decision equalizer, and a power module. An output terminal of the first amplification circuit, an input terminal of the second amplification circuit, and adjustment output terminals of the decision equalizer are connected through a signal line. The power module includes a first power supply unit and a second power supply unit. A minimum distance between the first power supply unit and the first amplification circuit is less than a minimum distance between the first power supply unit and the second amplification circuit, and a minimum distance between the second power supply unit and the second amplification circuit is less than a minimum distance between the second power supply unit and the first amplification circuit.
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