Importance

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Abstract

Methods, systems, apparatus, and articles of manufacture to validate timing constraints for an integrated circuit are disclosed. An example apparatus disclosed herein includes programmable circuitry to obtain an assumption property associated with a system on a chip (SoC) architecture, obtain a timing assertion associated with the SoC architecture, determine, using a formal property verification (FPV) tool, valid functional vectors and counter examples for the SoC architecture based on the assumption property and the timing assertion, and determine whether to accept a timing constraint based on at least one of the valid functional vectors or the counter examples, the timing constraint corresponding to the timing assertion.

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First Claim