Self-synchronous Side-Channel Attack Countermeasure
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United States of America
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Issued Date -
Dec 26, 2024
app pub date -
Jun 26, 2023
filing date -
Jun 26, 2023
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Abstract
An Attack Resilient Computation Circuit (ARCC) in an integrated circuit (IC) includes a first computation stage, a second computation stage, and security circuitry. The first computation stage is configured to process one or more signals so as to produce one or more outputs, the first computation stage having multiple signal propagation paths. The second computation stage is configured to receive and process the outputs of the first computation stage. The security circuitry is configured to generate a synchronization signal indicating that propagation of the signals in the first computation stage has completed, and to inhibit the second processing stage from processing the outputs of the first processing stage for a time interval derived from the synchronization signal.
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