POWER REDUCTION AND EFFECTIVE TIMING EXCEPTIONS HANDLING IN AT-SPEED CAPTURE

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20240427366A1
SERIAL NO

18337720

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Abstract

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According to an embodiment, a method for testing a scan chain is provided. The method includes receiving a first clock signal and a first scan enable signal and generating a second and third clock signal based on the first clock signal and the first scan enable signal. The third clock signal is delayed by a clock pulse from the second clock signal. The first, second, and third clock signal have the same duty cycle. The method further includes providing the second clock signal and the second scan enable signal to, respectively, a clock terminal and scan enable input of a first scan flip-flop of the scan chain. The method further includes providing the third clock signal and a third scan enable signal to, respectively, a clock terminal and a scan enable input of a last scan flip-flop of the scan chain.

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Patent Owner(s)

Patent OwnerAddress
STMICROELECTRONICS INTERNATIONAL N V1228 PLAN-LES-OUATES GENEVA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Srinivasan, Venkata Narayanan Greater Noida, IN 38 76
Srivastava, Umesh Chandra Greater Noida, IN 5 1
Vats, Shiv Kumar Greater Noida, IN 7 8

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