MEMORY DEVICES AND RELATED METHODS

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20240422967A1
SERIAL NO

18818251

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Abstract

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A microelectronic device comprises a memory array region, a control logic region underlying the memory array region, and an interconnect region vertically interposed between the memory array region and the control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically overlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically underlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region comprises control logic devices for the vertically extending strings of memory cells. The interconnect region comprises structures coupling the digit line structures to the control logic devices. Methods of forming a microelectronic device, and memory devices and electronic systems are also described.

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Patent Owner(s)

Patent OwnerAddress
LODESTAR LICENSING GROUP LLCEVANSTON IL

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Parekh, Kunal R Boise, US 328 3273

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