GPIO DRIVER WITH LOW LATENCY
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United States of America
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Issued Date -
Dec 19, 2024
app pub date -
Jun 10, 2024
filing date -
Jun 10, 2024
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention provides a GPIO driver including a control logic, a level shifter module and a post-driver. The control logic supplied by a first supply voltage is configured to receive an input signal to generate a first signal. The level shifter module is configured to receive the first signal to generate a second signal. The post-driver supplied by a second supply voltage is configured to receive the second signal to generate an output signal. When the first supply voltage is lower than the second supply voltage, the level shifter module performs a level-boosting operation to increase a voltage level of the first signal to generate the second signal; and when the first supply voltage is greater than the second supply voltage, the level shifter module operates as a buffer, and the voltage level of the second signal is the same as the voltage level of the first signal.
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