VERTICAL JUNCTION FIELD-EFFECT TRANSISTORS WITH SOURCE-DRAIN DIODE CELLS INTEGRATED AT DIE LEVEL

Number of patents in Portfolio can not be more than 2000

United States of America

APP PUB NO 20240421151A1
SERIAL NO

18742386

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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This disclosure relates to a semiconductor die and a method for fabrication of a semiconductor die. The disclosed semiconductor die comprises a substrate having a drain-cathode region, a plurality of trenches and mesas, a first anode trench, and a first floating closed loop mesa surrounding the first anode trench. The semiconductor die further comprises a first anode region under the first anode trench, a plurality of source regions extending from top surfaces into the plurality of mesas, and a plurality of gate regions extending along a bottom surface and portions of sidewalls of each of the plurality of trenches. The first floating closed loop mesa electrically isolates the first anode region from the plurality of gate regions, and the first anode region electrically couples to the plurality of source regions to integrate an anti-parallel diode cell within vertical junction field-effect transistors (JFETs).

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Patent Owner(s)

Patent OwnerAddress
UNITED SILICON CARBIDE INC7 DEER PARK DRIVE SUITE E MONMOUTH JUNCTION NJ 08852

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bhalla, Anup Princeton, US 325 5864
Li, Zhongda Chestnut Hill, US 11 27
Losee, Pete Clifton Park, US 1 0
Zhu, Ke Princeton, US 26 95

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