SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION AND SHALLOW TRENCH ISOLATION AND FABRICATING METHOD OF THE SAME
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Dec 19, 2024
app pub date -
Jul 7, 2023
filing date -
Jul 7, 2023
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A semiconductor device with a deep trench isolation and a shallow trench isolation includes a substrate. The substrate is divided into a high voltage transistor region and a low voltage transistor region. A deep trench is disposed within the high voltage transistor region. The deep trench includes a first trench and a second trench. The first trench includes a first bottom. The second trench extends from the first bottom toward a bottom of the substrate. A first shallow trench and a second shallow trench are disposed within the low voltage transistor region. A length of the first shallow trench is the same as a length of the second trench. An insulating layer fills in the first trench, the second trench, the first shallow trench and the second shallow trench.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully