Importance

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Abstract

A memory device comprising: a memory cell array including a plurality of memory cell strings coupled between a plurality of bit lines and a common source line, and a plurality of word lines coupled to the memory cell strings, and a control circuit configured to: repeat a program loop including a program pulse application operation and a verification operation until a program operation is successfully performed on memory cells that are coupled to a selected word line, a selected cell string, and the plurality of bit lines, additionally perform a channel precharge operation together with the program pulse application operation and the verification operation starting from a selected program loop, and vary a level of a precharge voltage applied to the common source line in the channel precharge operation according to an operation temperature.

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First Claim