MEMORY DEVICE FOR WAFER-ON-WAFER FORMED MEMORY AND LOGIC
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United States of America
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Issued Date -
Dec 19, 2024
app pub date -
Aug 30, 2024
filing date -
Aug 30, 2024
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Abstract
A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.
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