SYSTEM AND METHOD FOR MULTI-CHIP ISING MACHINE ARCHITECTURES
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United States of America
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Issued Date -
Dec 19, 2024
app pub date -
Nov 22, 2022
filing date -
Nov 22, 2022
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Abstract
A scalable Ising machine system comprises a plurality of chips, each chip comprising a plurality of N nodes, each node comprising a capacitor, a positive terminal, and a negative terminal, a plurality of N×M connection units, arranged in N rows and M columns, each connection unit comprising a set of reconfigurable resistive connections, each connection unit configurable to connect a pair of the N nodes via the reconfigurable resistive connections, and a plurality of interconnects, wherein each chip of the plurality of chips is communicatively connected all other chips of the plurality of chips via at least one interconnect. A method of calculating a Hamiltonian of a system of coupled spins is also disclosed.
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