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Abstract

There is provided an trapped ion processor comprising a DAC chamber, an ASIC, a digital control line between the DAC chamber and the ASIC and an analogue control line between the DAC chamber and the ASIC. The ASIC comprises a plurality of channels, each channel comprising a DC electrode, a first analogue memory cell and a second analogue memory cell. The DAC chamber comprises a DAC configured to generate an analogue signal and a DAC controller configured to generate timing control signals, the timing control signals comprising one or more sample timing signals to control when the analogue signal is sampled, as a voltage signal, by one or more of the plurality of the channels, and one or more synchronisation signals to control when the sampled voltage signal is applied to the respective DC electrode. The analogue control line transmits the analogue signal from the DAC to the plurality of channels and wherein the digital control line transmits the timing control signals from the DAC controller to the plurality of channels, the timing control signals controlling when the analogue signal is sampled, as a voltage, by either the first or the second analogue memory cell of each of a plurality of channels and controlling when the sampled voltage signal is applied to the respective DC electrode of each of a plurality of channels.

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First Claim