CLOCK GENERATION CIRCUIT, AND SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM USING THE CLOCK GENERATION CIRCUIT
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United States of America
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Dec 5, 2024
app pub date -
Sep 29, 2023
filing date -
Sep 29, 2023
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Abstract
A clock generation circuit includes a delay-locked circuit and a duty correction circuit. The delay-locked circuit generates a delay clock signal by delaying an input clock signal and update the delay time of the input clock signal. The duty correction circuit generates a first phase clock signal and a second phase clock signal by delaying the delay clock signal, and updates the delay time of the delay clock signal. The duty correction circuit can prevent or mitigate the delay time of the input clock signal and the delay time of the delay clock signal from being updated simultaneously.
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