CHIP COMPLEX WITH EMBEDDED INTERPOSER
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United States of America
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Issued Date -
Dec 5, 2024
app pub date -
May 29, 2024
filing date -
May 29, 2024
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Abstract
A chip complex is provided that includes at least a first IC die present in a first common tier, a passive interposer, and a plurality of IC dies present in a second common tier. The passive interposer includes an interconnect formed in a back end of the line (BEOL) region. The first IC die present in the first common tier are hybrid bonded to a top side of the passive interposer. The plurality of IC dies present in the second common tier are also hybrid bonded to a bottom side of the passive interposer.
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