INTERFACE CLOCK MANAGEMENT
Number of patents in Portfolio can not be more than 2000
United States of America
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Issued Date -
Dec 5, 2024
app pub date -
Jun 10, 2024
filing date -
Jun 10, 2024
priority date (Note) -
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status (Latency Note)
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Abstract
The timing of the synchronous interface is controlled by a clock signal driven by a controller. The clock is toggled in order to send a command to a memory device via the interface. If there are no additional commands to be sent via the interface, the controller suspends the clock signal. When the memory device is ready, the memory device drives a signal back to the controller. The timing of this signal is not dependent upon the clock signal. Receipt of this signal by the controller indicates that the memory device is ready and the clock signal should be resumed so that a status of the command can be returned via the interface, or another command issued via the interface.
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