VECTOR COMPUTATION APPARATUS, PROCESSOR, SYSTEM ON CHIP AND ELECTRONIC DEVICE
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United States of America
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Issued Date -
Dec 5, 2024
app pub date -
May 22, 2024
filing date -
May 22, 2024
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Abstract
A vector computation apparatus includes: a register unit including circuitry configured to store a first vector and a second vector respectively and divided into computation channels, each computation channel including a first array including first registers and a second array including second registers; a thread management unit including circuitry configured to determine at least one thread according to the corresponding relationship between at least one first element and at least one second element; and a computation unit including circuitry including a plurality of execution units, each execution unit includes circuitry configured to read a first element and a second element corresponding to each thread in the corresponding computation channel according to at least one thread, execute a modular operation between the first element and second element corresponding to the thread, and write a modular operation result in the first array or second array in the computation channel.
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