Adaptive Power Tuning in a Successive Approximation Analog-to-Digital Converter
Number of patents in Portfolio can not be more than 2000
United States of America
Stats
-
N/A
Issued Date -
Nov 28, 2024
app pub date -
May 23, 2024
filing date -
May 23, 2024
priority date (Note) -
Published
status (Latency Note)
Importance
Abstract
A Successive Approximation Analog-to-Digital Converter (SAR_ADC) and method of operating the same are provided. Generally, the SAR_ADC includes a comparator having a first input to receive an input voltage (VIN), and a second input coupled to a n-bit capacitive digital-to-analog converter (DAC) to receive a voltage (VDAC), a Successive Approximation Register (SAR) coupled to a comparator output to provide n digital control signals to the DAC, and to store and output an n-bit binary-number approximating VIN, and a reference buffer to provide a voltage (VREF) to the DAC. The DAC sequentially drives each capacitance beginning with a most significant bit towards VREF, while the comparator compares the resulting VDAC to VIN, and the SAR sets or clears a current bit represented by the capacitance driven. The reference buffer includes adaptive power tuning to dynamically tune a drive-strength of the reference buffer based on the current bit.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully